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NOIL1SN3000A
Table 11. AFE AND ADC PARAMETERS
Parameter
Total AFE + ADC latency
Total AFE + ADC power
(32 channels = 64 AFE + ADC)
Parameter Value (typical)
44 master clocks
400 mW (at 2.5 V)
Comment
5.5 ADC clocks = 1/8 of master clk
160 mA
Protocol Layer
Digital data from the ADCs is reorganized in the protocol
layer before it is transferred to the LVDS drivers. Perform
these operations in the protocol layer:
? Multiplexing of two ADCs to one output data channel.
? Adding the cyclical redundancy check (CRC)
checksum to the data stream. This operation is done
row by row. A new CRC checksum is calculated for
every new row that is readout.
? Switching readout mode. The LUPA3000 sensor is
programmed to operate in two other readout modes:
training and test image modes. These modes
synchronize the readout circuitry of the end user with
the sensor.
? Assembling the data stream of the synchronization
channel.
lsb
datain
CRC
LUPA3000 implements a CRC for each row (line) of
processed data to detect errors during the high speed
transmission. CRC provides error detection capability at
low cost and overhead.
The CRC polynomial implemented for LUPA3000 is:
x^8+x^6+x^3+x^2+1.
The CRC result is transmitted with the original data.
When the data is received (or recovered), the CRC algorithm
is reapplied and the latest result compared to the original
result. If a transmission error occurs, a different CRC result
is obtained. The system then chooses to operate on the
detected error or has the frame resent.
The CRC shift register is initialized with logic 1s at reset
to improve bit error detection efficiency.
Referring to Figure 11, the CRC value is calculated for
each row and inserted into the serial data stream. Bit 0 of SPI
register 71 (decimal) is an enable bit to insert the CRC
checksum. CRC is enabled when a logic 1 is written to this
bit. This is the default (POR) value. Bit 1 of this register
allows calculation and insertion of a CRC checksum to the
“synchronization” channel. No checksum is attached by
default.
msb
(msb first)
x0
x1
x2
x3
x4
x5
x6
x7
x 8 + x 6 + x 3 + x 2 + 1
Figure 11. Equivalent Polynomial Representation in Serial Format
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